In today's rapidly advancing semiconductor manufacturing industry, there is a continued drive to produce feature sizes of smaller and smaller dimensions. Conductive lines are most critical to any integrated circuit or other semiconductor device as they interconnect the active devices and carry current and signals that enable the semiconductor device to operate. The drive to continue to decrease feature size applies to conductive lines. As levels of integration continue to increase, it becomes even more advantageous to form increasingly smaller conductive lines, and to form conductive lines in close proximity to one another and without shorting to one another. This applies to conductive lines, also referred to as leads, that are adjacent one another and also to conductive lines that are aligned end-to-end, i.e. longitudinally.
Damascene techniques and other patterning techniques are available to define conductive lines and other features and various processes are available to form the actual conductive lines. All of these techniques have limitations with respect to the minimum dimensions of the conductive features that can be achieved. There are also limitations with respect to minimum spacing differences between adjacent conductive features that can be achieved without shorting.
The present disclosure provides an advancement that enables the definition and formation of increasingly smaller conductive lines and increasingly tighter spaced conductive features.